This invention generally relates to ultra thin gate oxide manufacture and more particularly to an improved method and apparatus for reducing oxidation furnace system contaminants to improve gate oxide uniformity.
In the semiconductor fabrication process, one of the more important processing steps is the formation of a high quality insulating gate oxide layer in the field of semiconductor devices fabrication. Many broad categories of commercial devices, such as electrically erasable programmable read only memories (EEPROMs), dynamic random access memories (DRAMs), and more recently, even high-speed basic logic functions, owe their commercialization to the reproducibility of high quality, very thin oxide layers. High quality dielectrics are needed in such devices to achieve satisfactory device performance both in terms of speed and longevity.
Hot carrier effects and sub-threshold leakage currents are problematic in short channel devices. One technique to combat short channel effects has involved the scaling of gate dielectrics. To compensate for the potentially lower drive currents for a given short channel device, conventional silicon dioxide gate oxide layers are made as thin as possible to maximize drive current. However, the scaling of silicon dioxide gate dielectric layers has introduced another set of problems. For example, thin silicon dioxide layers have been historically difficult to fabricate with a uniform thickness across a given water area, from wafer to wafer and from lot to lot. In addition, as the thickness of silicon dioxide is scaled downward, the potential for reliability problems associated with dielectric breakdown and hot and cold carrier injection degradation increases. Hot and cold carrier degradation can significantly reduce device performance, while dielectric breakdown can lead to complete device failure.
Ultra-thin gate oxides (less than about 30 Angstroms) are required for achieving small and fast device technology, for example, at device dimensions below about 0.13 microns. Uniformity is one of the major challenges in ultra-thin gate oxide fabrication since such uniformity is strongly correlated with gate oxide integrity. Most conventional gate insulating layers are pure SiO2 (silicon dioxide) films formed by thermal oxidation. Others employ a combination of a high temperature deposited SiO2layer on a thermally grown layer.
Generally, silicon dioxide layers can be grown within a temperature range from about 400xc2x0 C. to about 1150xc2x0 C. The growth process may be carried out in resistance-heated furnaces or in rapid thermal process chambers heated by, for example, tungsten-halogen lamps. Typically, either a horizontal or a vertical furnace tube is used for resistance heated furnaces where after loading a batch of process wafers into a furnace, the furnace is heated to (ramped-up) a temperature suitable for oxidation of silicon. The process wafers are then held at the elevated temperature (annealed) for a period of time to grow an oxide layer and then cooled (ramped-down) to a lower temperature.
Silicon dioxide (SiO2) can be grown by either a dry oxidation process or a wet oxidation process. In a dry oxidation process, oxygen is mixed with an inert carrier gas such as nitrogen, and is passed over a batch of process wafers at an elevated temperature. In a wet oxidation process, the process can be carried out by catalytically combusting hydrogen and oxygen in a pyrogenic steam oxidation process to form a water vapor/oxygen mixture which is then supplied to the furnace reactor tube at a predetermined elevated temperature.
FIG. 1 shows a typical pyrogenic steam oxidation system 10 including a gas feed line system according to the prior art. As shown in FIG. 1, a pyrogenic steam oxidation process may be carried out in vertical furnace tube, for example, a quartz boat 12 for holding several process wafers e.g., 14, surrounded by a tubular quartz process chamber 16, being externally surrounded by typically about 3 or more resistance heaters (not shown). Inside the quartz process chamber 16 wafer boat 12 holds a batch of silicon wafers e.g., 14 with the major surface areas arranged horizontally and stacked vertically to minimized thermal gradients. Source gases, including for example, individually fed and mixed, or pre-mixed mixtures of, for example, N2 and O2 18A, and N2, O2, and H2, 18B, are fed through a burner heated area 28A including a catalyst core for combusting H2 and O2 to produce water which is carried with other source gases, e.g., N2, by gas source feed line 20A to an entry point, e.g., valve 19A adjacent the top of the quartz reactor chamber 16 at inlet 20B to pass over the process wafers e.g., 14. Water vapor is thus formed by reaction between hydrogen and oxygen, acting as an oxidizing medium to produce SiO2 on the silicon wafers e.g., 14. Unused reactants and reaction by-products are passed out through exhaust vacuum line 22A.
Another reactant including chlorine source gas dichloroethylene (DCE) gas source 24A is frequently fed through a separate gas feed line 26A including passing through a second burner heated area 28B to combust the chlorine source gas to form gaseous chlorine species. Source gases, including for example, individually fed and mixed, or pre-mixed mixtures of, for example, N2, O2, and NO, 21A, and N2 and H2, 21B, are fed through an burner heated area 28B area to provide combustion and carrier gases for the chlorine gas source 24A. For example, chlorine is frequently used as an additive in forming thin oxide layers as it has been found to neutralize charge accumulation at the Si/SiO2 interface and additionally has the beneficial property of immobilizing or gettering mobile ionic contaminants, for example, metal ions present in the reactor chamber. In addition, chlorine containing gas, for example, DCE, is also used as a step in a periodic cleaning process where the quartz boat, chamber and other components are exposed to DCE and chlorine as part of the periodic cleaning process.
According to the prior art an inert gas source 21C, for example nitrogen, in gaseous communication with gas feed line, e.g., 26B typically disposed between the heated burner area 28B and the reactor chamber 16 through a gas valve 19B to allow purging of the chlorine containing gas residue remaining in the gas feed line 26A through the reactor chamber 16 and out exhaust vacuum line 22A. A problem with this arrangement is that the reactor chamber may become further contaminated by re-deposition with chlorine containing residues and/or water vapor leading to non-uniform oxide film growth.
Controlling the growth of an ultra-thin oxide layer of less than about 30 Angstroms is difficult to control. One reason for such difficulty is simply the short pyro-time required for depositing such ultra-thin oxide layers. Another reason is the high annealing temperatures required to treat such ultra-thin oxide layers to obtain a high quality oxide. The annealing process for the ultra-thin oxide layers typically requires temperatures of about 1000xc2x0 C. At this temperature, any residual contaminants including chlorine or water containing residues present in the reaction chamber or gas feed conduits leading to the reaction chamber may be a source of contamination and cause unexpected non-uniform oxide growth on the wafers thereby leading to both within wafer, wafer to wafer, and successive oxidation run non-uniformity of the oxide layer.
It would therefore be advantageous to develop a furnace system for growing silicon dioxide layers including gate oxides whereby moisture or other contaminants including chlorine containing residues present within the furnace system are reduced to allow for more uniform oxide growth leading to more reliable electrical performance and successful scale-down of semiconductor structures.
It is therefore an object of the invention to provide a furnace system for growing silicon dioxide layers including gate oxides whereby moisture or other contaminants including chlorine containing residues present within the furnace system are reduced to allow for more uniform oxide growth leading to more reliable electrical performance and successful scale-down of semiconductor structures while overcoming other shortcomings in the prior art.
To achieve the foregoing and other objects, and in accordance with the purposes of the present invention, as embodied and broadly described herein, the present invention provides a method for a method and apparatus for improving a uniformity of a thermally grown silicon dioxide layer.
In a first embodiment, the method includes thermally growing a layer over the exposed silicon portions including silicon dioxide according to a thermal oxide growing process; exposing the gas reactant feed lines to reactant gases during at least one of the step of thermally growing a layer and a cleaning process following the step of thermally growing a layer; and, purging the gas flow pathways to bypass the reactor chamber with at least one purge gas source including an inert gas to remove residual reactant gas contaminants to improve a subsequently thermally grown silicon dioxide layer.
These and other embodiments, aspects and features of the invention will be better understood from a detailed description of the preferred embodiments of the invention which are further described below in conjunction with the accompanying Figures.